May. 10
Final Program
(presentation is
20 minutes including Q&A)
Apr. 17
Tentative program
University of
Calgary map is here
Mar.
20
Authors have notified about
acceptance.
Guide-Line of the Camera-Ready Manuscript is here
(FINAL
Program)
10:30-10:35
Opening Remark
ULSIWS Chair, Yasushi Yuminaka (Gunma Univ.,
Japan)
Session 1: New Algorithm and
Logic
10:35-10:55
TRISAT - A
SAT-solver using ternary-valued logics
Martin Johnson (Massey
Univ., New Zealnad) and
Christian Posthoff (The Univ. of The West Indies,
Trinidad & Tobago)
10:55-11:15
Binary Polynomial Expansions based on New Fastest
Linearly
Independent
Transforms
Cicilia C. Lozano, Bogdan J.
Falkowski (Nanyang Tech. Univ., Singapore)
and Susanto Rahardja
(Institute for Infocomm Research, Singapore)
11:15-13:15 Lunch
Session 2: Invited Session
13:15-14:00
TMR-Based Logic-in-Memory
Circuit and Its Application
Takahiro Hanyu, Akira Mochizuki and
Mitsuru Ibuki,
(Tohoku Univ., Japan)
Session 3:
New-Paradigm VLSI Circuits and Systems
14:00-14:20
A high-speed data transmission technique using Tomlinson-Harashima
Preconding(THP)
Yosuke IIJIMA (Univ. of Tsukuba, Japan) and
Yasushi YUMINAKA (Gunma Univ., Japan)
14:20-14:40
0.2V-Swing Multiple-Valued Differential-Pair Circuit
and Its
Application to Arithmetic VLSI
Akira Mochizuki and Takahiro Hanyu
(Tohoku Univ., Japan)
14:40-15:00 Coffe Break
Session 4: Reversible and Quantum Logic Design
15:00-15:20
Stochastic modeling of
BDD-based nanoscale logic circuits
S. N. Yanushkevich and S.D.
Kiselev (Univ. of Calgary, Canada)
15:20-15:40
Combining Evolutionary and Exhaustive Search to find the Least
expensive Quantum Circuits
Martin Lukac, Marek Perkowski,
(Portland state Univ., USA)
15:40-16:00
Reversible Logic Synthesis Example using a Transformation Based
Algorithm
B. Gergel and J. Rice (Univ. of Lethbridge,
Canada)
16:00-16:20
Synthesis of reversible
circuits with small ancilla bits for large
irreversible incompletely
specified multi-output Boolean functions
Christopher Stedman, Bruce Yen and Marek Perkowski,
(Portland state Univ., USA)
16:20 Closing
18:00 ISVML
reception
For ULSIWS2004, visit: http://www.el.gunma-u.ac.jp/~yuminaka/ULSIWS2004.htm
For additional information contact:Associate Professor
Yasushi YUMINAKA, ULSIWS Chair
Department of Electronic Engineering
Gunma University, Japan
Email: yuminaka@el.gunma-u.ac.jp