(Program)
9:00-9:05
Opening Remark
ULSIWS Chair, Yasushi Yuminaka (Gunma Univ., Japan)
9:05- 9:25
High-speed data transmission techniques using raised cosine approximation signaling
Yasushi Yuminaka and Yusuke Tsubota (Gunma Univ., Japan)
9:25- 9:45
High-level Synthesis of Asynchronous Circuits and Its Optimization
Atsushi Matsumoto, Tomohiro Yoneda, and Takahiro Hanyu
(Tohoku Univ., and National Institute of Informatics, Japan)
9:45-10:05
On the Potential of CMOS Recharged Semi-Floating Gate
Devices used in Balanced Ternary Logic
Henning Gundersen (University of Oslo, Norway)
10:20-10:40
An Ultrahigh-Speed Full Adder Using Resonant-Tunneling Logic Gates
Takao Waho, Hiroki Okuyama, Tomihiko Ebata, and Ryousuke Kato (Sophia Univ.,
Japan)
10:40-11:00
Power Analysis of RSA Processors with High-radix Montgomery Multipliers
Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, and Akashi Satoh
(Tohoku Univ. and National Institute of Advanced Industrial Science and Technology,
Japan)
11:00-11:20
The affine gates and affine polarities for quantum
arrays with small costs
Sazzad Hossain and Marek Perkowski (Portland State University, USA)
11:20-11:40
Using Fuzzy Quantum Logic to learn facial gestures of a Schrodinger Cat
puppet for robot theatre
Arushi Raghuvanshi and Marek Perkowski (Portland State University, USA)
12:00 Lunch
For additional information contact:
Associate Professor
Tetsuya UEMURA, ULSIWS Chair
Div. of Electronics for Informatics
Hokkaido University, Japan
Email: uemura@ist.hokudai.ac.jp